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Smart Verification

In the semiconductor industry, we build the technology of tomorrow with tools that might have been created the “day before yesterday.” Despite our contributions to the future, our industry often remains stuck with outdated technologies. There are numerous reasons for this inertia, which many readers might be familiar with, as it reflects a general reluctance to adopt new technologies, techniques, or innovations.

Consider the following tools and reflect on whether you are utilizing the latest advancements in your design and verification flow:

  • Version control systems
  • Operating Systems (OS) for running EDA tools
  • Continuous Integration (CI)
  • Communication and documentation tools
  • Collaboration tools
  • Simulators/Emulators
  • Scripting languages
  • Design and verification languages/methodologies
  • Etc.

With the AI momentum gaining traction worldwide, I am curious about how these technological advancements in AI are being utilized or planned to be used in our semiconductor industry.

Last year (2024) I’ve watched three presentations from the largest EDA vendors: Cadence, Siemens, and Synopsys, showcased during the Verification Futures Conference UK, held on June 18, 2024. These presentations provided insight into how these vendors are leveraging AI and their AI roadmaps. Under the AI umbrella, terms like Generative Artificial Intelligence (GenAI), Machine Learning (ML), and Natural Language Processing (NLP) were frequently mentioned.

The presentations are publicly available on YouTube:

Here is the full agenda from the Verification Future Conference UK 2024.

These presentations explore the transformative impact of AI on verification productivity within the electronic design automation (EDA) industry.

  1. Cadence: “AI and GenAI for Verification Productivity” Cadence’s presentation discusses the increasing complexity of designs, the surge in new designs, and the human factor (engineering talent shortage) that exacerbate current technological challenges. It showcases how AI, through GenAI, optimizations, and accelerated computing, can mitigate these challenges. Key areas of improvement include stimulus generation, triaging failures, bug prediction, root cause analysis, and more. They also introduced a Copilot-like tool with a chat interface to help users write assertions for designs using integrated documentation.
  2. Siemens: “Introducing Smart Verification: Unleashing the Potential of AI within Functional Verification” Siemens introduces the concept of Smart Verification, emphasizing the increasing complexity and skills shortage in the industry. They argue that a new level of productivity can be achieved by complementing traditional methods with AI, though this requires expertise in both EDA and AI, along with extensive data. Siemens currently offers tools for Pattern Analysis and Cross Hole Analysis, and they have a roadmap for tools targeting root cause prediction, bad commit prediction, signature prediction, smart regression, code generation using Copilot Smart Creation (UVM TB, RTL, assertions), and coverage optimization.
  3. Synopsys: “Autonomous Verification – Are We There Yet?” Synopsys’s presentation examines the current state and future prospects of autonomous verification, comparing verification automation levels to driving automation levels. They present a graph showing how TTM, engineers, and design complexity influence silicon realization, considering respins due to logical/functional issues. Key areas where AI can help include coverage closure and debug, supported by a data continuum. Synopsys also introduced an RTL copilot for code generation and discussed the potential of GenAI to transform English specifications into machine-readable specifications. Challenges highlighted include the lack of public data, costs of private LLMs, and LLM hallucinations.

Collectively, these presentations illustrate the significant progress being made in leveraging AI to revolutionize verification processes, highlighting both the current achievements and the future potential of AI in the EDA industry.

Interestingly, a few days after the conference, Brian Bailey posted an article addressing the same issues highlighted by major EDA vendors. His article, “Verification Tools Straining to Keep Up” published in Semiconductor Engineering, discusses the growing challenges faced by verification engineers in the semiconductor industry and suggests AI as a potential solution.

This underlines the urgent need for our industry to embrace modern technologies and innovative approaches to stay ahead in the rapidly evolving landscape.



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